Flexible Circuits and Architectures for Ultralow Power
| Autor: | John Lach, Mateja Putic, Benton H. Calhoun, Sudhanshu Khanna, Joseph F. Ryan |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Digital electronics
Engineering business.industry Subthreshold conduction Circuit design Electrical engineering Integrated circuit Dynamic voltage scaling law.invention law Low-power electronics Electronic engineering Electrical and Electronic Engineering business Field-programmable gate array Low voltage |
| Zdroj: | Proceedings of the IEEE. 98:267-282 |
| ISSN: | 1558-2256 0018-9219 |
| Popis: | Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-V DD, multi-V DD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort. |
| Databáze: | OpenAIRE |
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