| Popis: |
A spacer patterning technology (SP) has the possibility of extending optical lithography to below 40nm half-pitch devices. Since the spacer patterning process necessitates somewhat more complicated wafer process flow, the CD variation on wafers involves more process error sources compared with conventional exposure patterning process. This implies that, for the spacer patterning process innovation in determining specifications for each unit process is requried. In particular, it is important to determine mask-related specifications in order to select high-end mask fabrication strategies for mask writing tools, mask process development, materials, inspection tools, and so on. The purpose of this paper is to discuss how to consider mask specification in spacer patterning process for 40nm half-pitch and beyond. |
