Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates

Autor:	J. Juan-Chico, E. Ostua, David Guerrero Martos, Alejandro Millán Calderón, Paulino Ruiz de Clavijo, Manuel J. Díaz, J. Viejo
Rok vydání:	2005
Předmět:	Consumption (economics) Finite-state machine Electrical load Power consumption Computer science business.industry Logic gate Electronic engineering State (computer science) Telecommunications business Power (physics)
Zdroj:	Lecture Notes in Computer Science ISBN: 9783540290131 PATMOS
DOI:	10.1007/11556930_35
Popis:	In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 μm, AMS 0.35 μm, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ed64555f30f7142b663bb52b63ee9080 https://doi.org/10.1007/11556930_35 Zobrazit plný text záznamu