A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Autor:	Anuj Rao, Ritchie Zhao, Khalid Al-Hawaj, Chun Zhao, Shaolin Xie, Ronald G. Dreslinski, Christopher Batten, Ian Galton, Luis Vega, Zhiru Zhang, Julian Puscar, Austin Rovinski, Paul Gao, Steve Dai, Tutu Ajayi, Michael Taylor, Christopher Torng, Bandhav Veluri, Aporva Amarnath, Dustin Richmond, Scott Davidson
Rok vydání:	2019
Předmět:	Router Computer science business.industry 020208 electrical & electronic engineering 02 engineering and technology ComputerSystemsOrganization_PROCESSORARCHITECTURES 021001 nanoscience & nanotechnology Giga Manycore processor CMOS RISC-V 0202 electrical engineering electronic engineering information engineering Benchmark (computing) Bandwidth (computing) Node (circuits) 0210 nano-technology business Computer hardware
Zdroj:	VLSI Circuits
DOI:	10.23919/vlsic.2019.8778031
Popis:	This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ed4f40220e0707c0642b271415d5476c https://doi.org/10.23919/vlsic.2019.8778031 Zobrazit plný text záznamu