| Autor: |
Ailin Zhang, Yan Wu, Junwu Zhang, Andy Xie, Macro Wu, Honyin Chiu, Y.B. Zou, Simon He, Thomas Zhao, Roy K.-Y. Wong, Henry Liao, Jeff Zhang, Chunhua Zhou, Martin Zhang, Seiya Li, John Lee, Chen Po-Hui |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD). |
| Popis: |
A novel strain engineering is reported to realize enhancement-mode high electron mobility transistors (HEMTs) with ultralow specific on-resistance ( $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$ ) fabricated on 200 mm CMOS-compatible process platform. In this scheme, a strain enhancement layer deposited on the access region of HEMT by a low cost CVD process is demonstrated to reduce $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$ . As comparing to 100 V-rated HEMT without the strain layer, HEMT with the strain layer features comparable $\boldsymbol{V}_{\mathbf{th}}$ of +1.5 V but significant $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$ reduction of 24% and 28% at ambient temperatures of 25 °C and 150 °C, respectively. The proposed device exhibits the off-state drain-to-source breakdown voltage increases about 12%. System verification shows that high efficiency of 92.7% which is higher than the state-of-art Si MOSFET about 3% with stable burn-in performance. This work achieves a record low $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$ in 100 V rating commercially available GaN and Si power transistors. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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