Achieving Simplified Biasing Conditions with Pin Reduction Approach to enhance Static Fault Localization Capability
| Autor: | D. Nagalingam, Sj. Moon, Hp. Ng, J.C. Lam, Y.S. Tam, Z. H. Mai, A. C. T. Quah, C.Q. Chen, G. B. Ang, K.H. Yip, P.T. Ng |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Computer science media_common.quotation_subject 020208 electrical & electronic engineering Biasing 02 engineering and technology Integrated circuit Replicate 01 natural sciences Iddq testing Reliability engineering law.invention Debugging law 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Failure mode and effects analysis media_common Leakage (electronics) |
| Zdroj: | 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). |
| DOI: | 10.1109/ipfa.2018.8452583 |
| Popis: | Successful fault localization is heavily dependent on the ability to replicate the failure mode in the analytical scanning optical microscope (SOM) system for defect isolation. However, typical SOM configuration with confined stage space is limited to about 4 probes – 4 SMUs resources for bench measurement. This has impeded the successful debug of functional IDDQ/powerdown leakage failure which may require higher pin counts to enter into leakage mode. In this paper, the static fault localization capability of such failures is enhanced with an engineering approach to simplify the biasing conditions for static debug within the SOM system with limited test resources. This is especially useful in a foundry environment that manufactures a wide variety of products from differentiated process lines. Several case studies were described to demonstrate how this optimized electrical FA flow was applied with great success to debug multiple challenging low yield functional leakage issues. |
| Databáze: | OpenAIRE |
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