An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling

Autor:	Peter Mayer, Ronny Schneider, Sven Piatkowski, Gabriele Piscopo, Daniel Lauber, David K. Ovard, Marcos Alvarez-Gonzalez, Marc Walter, Natalija Jovanovic, Manfred Plan, Stefan Dietrich, Thomas Hein, Jorg Weller, Timothy M. Hollis, Fabien Funfrock, Martin Bach, Stephan Rau, Jan Pottgiesser, Shih Nern Wong, Juan Ocon-Garrido, Michael Richter, K. Peter Pfefferl, Mani Balakrishnan, Andreas Schneider, Cristian Chetreanu, Casto Salobrena Garcia, Wolfgang Spirkl, Maksim Kuzmenka, Filippo Vitale, Martin Brox, Andrea Sorrentino, Jens Polney, Milena Ivanov
Rok vydání:	2022
Předmět:	Dynamic random-access memory Computer science business.industry Transistor Process (computing) High Bandwidth Memory law.invention Pulse-amplitude modulation law Bandwidth (computing) Electrical and Electronic Engineering business Computer hardware Dram Efficient energy use
Zdroj:	IEEE Journal of Solid-State Circuits. 57:224-235
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2021.3104093
Popis:	Demand for dynamic random access memory (DRAM) bandwidth has outpaced DRAM transistor performance. Given the options of major process investment to scale beyond sixth-generation graphics double-data-rate (GDDR6) or replace GDDR6 with costly high bandwidth memory (HBM), this article presents a solution that simultaneously increases pin and energy efficiency through the integration of four-level pulse amplitude modulation (PAM-4) into the single-ended memory interface. Building upon the existing GDDR6 architecture, evolutionary modifications to input, output, clocking, and data path, along with the component package design, enable a per-pin data rate of more than 22 Gb/s.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::ec2abeef90880b64e64b2b12161150d1 https://doi.org/10.1109/jssc.2021.3104093 Zobrazit plný text záznamu