IBM POWER9 memory architectures for optimized systems
| Autor: | James A. Marcella, Jeffrey A. Stuecheli, Brad W. Michael, Stephen J. Powell, John Steven Dodson, William J. Starke, Eric E. Retter |
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| Rok vydání: | 2018 |
| Předmět: |
020203 distributed computing
Hardware_MEMORYSTRUCTURES General Computer Science Chipset Computer science Bandwidth (signal processing) Graphics processing unit 020206 networking & telecommunications 02 engineering and technology Computer architecture Memory architecture 0202 electrical engineering electronic engineering information engineering IBM Physical design Architecture Host (network) |
| Zdroj: | IBM Journal of Research and Development. 62:3:1-3:13 |
| ISSN: | 0018-8646 |
| Popis: | The IBM POWER9 processor chipset provides a variety of system memory architecture interfaces to enable highly differentiated system offerings: a high bandwidth, high capacity, highly reliable, buffered architecture; a compute-density-optimized direct DDR attach architecture; heterogeneous integration of graphics processing unit memory into the host system memory; and an agnostic, flexibly attached SCM architecture. In this paper, we explore these architectures and the targeted optimizations they provide for various classes of workloads. We also explore the development synergies and semiconductor physical design tradeoffs associated with the varying implementations, and finally, we describe several hypothetical systems that could be constructed by utilizing these memory architectures. |
| Databáze: | OpenAIRE |
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