An area-efficient PLL architecture in 90-nm CMOS
| Autor: | Peter Jean Woo Lim |
|---|---|
| Rok vydání: | 2005 |
| Předmět: |
Engineering
business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Capacitance law.invention Phase-locked loop Capacitor CMOS Parasitic capacitance Hardware_GENERAL law PLL multibit Hardware_INTEGRATEDCIRCUITS Electronic engineering business Active filter Hardware_LOGICDESIGN Jitter |
| Zdroj: | Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.. |
| DOI: | 10.1109/vlsic.2005.1469330 |
| Popis: | An area-efficient phase-locked loop (PLL) design is presented. The PLL architecture allows the implementation of a charge-pump based PLL stabilization filter network using sample-reset techniques and a total loop-capacitor equivalent to a typical ripple-reduction capacitor. Implemented in a logic 90-nm CMOS process, this PLL integrates a total loop capacitance of 3 pF using parasitic metal-metal capacitor structures, measures 160 /spl times/ 171 /spl mu/m and exhibits a measured rms period jitter of 1.68 ps at 2.5 GHz. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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