TLP IV characterization of a 40 nm CMOS IO protection concept in the powered state
| Autor: | Benjamin Orr, Krzysztof Domanski, Harald Gossner, David Pommerenke |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Engineering Electrostatic discharge business.industry Electrical engineering 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 01 natural sciences Characterization (materials science) CMOS 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering State (computer science) business Cmos process |
| Zdroj: | 2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD). |
| DOI: | 10.1109/eosesd.2016.7592566 |
| Popis: | In this paper, the interaction between the ESD protection concept and a powered output driver in a 40 nm CMOS process are investigated and characterized by TLP. By using IO test chips designed for HBM and CDM validation, the IV behavior of the pin is measured with the driver placed into various states. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|