| Popis: |
The generation of accurate simulation models for the interconnect and devices on a bus is becoming increasingly important in high-speed, high-performance digital systems. The simulation model should accurately predict the performance of the system over the entire operating frequency range. A method of modeling a high-speed bus is described in this paper. The measurement and modeling environments are discussed The methodology presented includes measurement of the interconnect and devices' frequency response using a Vector Network Analyzer (VNA), creating an empirical model for the bus, then optimizing the model parameters to fit the simulated response of the model with the measurement response using HSPICE. The use of this methodology in creating component and system models is described. The measured and simulated responses indicate potential noise problems such as impedance discontinuities and resonances, at well as other noise sources in the system. Careful analysis of the responses helps reveal the causes. Hence these can be eliminated quite readily. A memory bus that has a peak bandwidth of 600 Mbits/sec/wire (Megabits per second per wire) is measured using the methodology presented in this paper, and a detailed model created. This model is then optimized using HSPICE. The results are discussed. |
