Automated layout-integrated sizing of a 2.45 GHz differential-drive rectifier in 28 nm FDSOI CMOS
| Autor: | Denis Flandre, Jean-Pierre Raskin, David Bol, Pierre-Antoine Haddad, Francois Stas |
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| Rok vydání: | 2017 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering Electrical engineering 020206 networking & telecommunications 02 engineering and technology Sizing Power (physics) Rectifier Ultra high frequency CMOS MOSFET Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Place and route Parasitic extraction business |
| Zdroj: | 2017 IEEE Wireless Power Transfer Conference (WPTC). |
| Popis: | Rectifiers are considered key analog blocks to power the energy-autonomous wireless applications envisioned by the Internet-of-Things. However, their design routine is still a time-consuming process as the layout step requires human intervention at each iteration of the optimization phase. The layout parasitic effects (e.g. well-proximity effects) introduced by this step can have a non-negligible impact on circuit performances, especially when targeting high-efficiency operation at UHF in the ultra-low power range, where parasitics have a higher impact. In this paper, we propose an automatic sizing and layout integrated methodology, based on commercial digital place and route tools, to optimize the cross-coupled/differential-drive rectifier architecture, including post-layout verification, in an advanced 28nm FDSOI CMOS process. A genetic and a gradient optimization methods are compared to increase the time-efficiency of the methodology. A 3-stage rectifier is optimized, providing 1.17 μW under 1 μΑ load at 2.45 GHz with 68% efficiency. |
| Databáze: | OpenAIRE |
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