Duet: an accurate leakage estimation and optimization tool for dual-V/sub t/ circuits
| Autor: | Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards, David Blaauw, Rajendran Panda |
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| Rok vydání: | 2002 |
| Předmět: |
Digital electronics
Very-large-scale integration Engineering business.industry Transistor Spice Hardware_PERFORMANCEANDRELIABILITY law.invention Computer Science::Hardware Architecture Hardware and Architecture law Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Standby power Software Hardware_LOGICDESIGN Electronic circuit Leakage (electronics) |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10:79-90 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/92.994980 |
| Popis: | Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V/sub t/ processes. The approach is the first to consider the assignment of both the V/sub t/ and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device. |
| Databáze: | OpenAIRE |
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