Breaking the barrier of parallel simulation of digital systems

Autor:	Jack V. Briner, John L. Ellis, Gershon Kedem
Rok vydání:	1991
Předmět:	Adder Speedup Parallel processing (DSP implementation) Computer science Asynchronous communication Synchronization (computer science) Data synchronization Parallel computing Clock synchronization Sequential algorithm Synchronization
Zdroj:	DAC
DOI:	10.1145/127601.127669
Popis:	We show that digital systems contain significantly more parallelism than previously thought. By reducing the dependency on time as the mechanism for synchronization. significant speedups are possible. By using asynchronous control ad Virtual Time synchronization with Lazy Cancellation, limited component sizes, special clock distribution and bounding windows, we get up to 23X speedup on a 32 processor system over a good sequential algorithm for mixed-level simulation.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::eac9c4e5e13396145810fb8e0f7fd22c https://doi.org/10.1145/127601.127669 Zobrazit plný text záznamu