| Popis: |
The dielectric material used to fill trenches in Shallow Trench Isolation (STI) of transistors, is key to device performance. This paper (a) evaluates the integration of currently available dielectric technologies and (b) designs an optimized process scheme for 0.25 /spl mu/m node and beyond. A detailed study of LPCVD TEOS, SACVD oxide, Hydrogen-Silsesquioxane SOG (HSQ) and ICP (Inductively Coupled) HDP (High Density Plasma) CVD oxide, for STI, is presented for the first time. A novel ICP HDP-CVD process scheme is shown to have the advantages of single step, low thermal budget and high throughput as well as provide good gap-fill, low HF etch rate, low moisture uptake, low shrinkage with annealing, low diode reverse leakage and isolation at 0.3 /spl mu/m spacing. |
