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A 3D stacked IC is made of multiple dies possibly with heterogeneous process technologies. Therefore, the die-to-die variation between the stacked dies creates on-package variation in a 3D chip. In this paper, we analyze the effect of on-package variation on the 3D clock trees and address the problem of on-package variation aware layer embedding in 3D clock tree synthesis. The layer embedding problem is divided into two sub-problems: clock node embedding and clock edge embedding. While the clock node embedded problem has been intensively investigated by the previous 3D clock tree synthesis flows because the solution directly determines the TSV allocation, the clock edge embedding problem has not been fully addressed yet. We show in this work that a careful clock edge embedding can greatly reduce the impact of on-package variation on the 3D clock skew , thereby enhancing chip yield, and propose a two-step solution to the problem of on-package variation aware layer embedding of clock edges. Specifically, we formulate the edge embedding problem into a problem of maximizing the sharing of layers among the clock paths to minimize the impact of on-package variation globally and solve it efficiently, followed by applying a fine-grained refinement technique to balance the clock latency locally among the clock paths. From the experiments with Benchmark circuits, we confirm that compared to the results produced by the conventional on-package variation unaware layer embedding of clock edges, the proposed algorithm is able to improve the chip yield by 6.2–25.8% and 5.3–44.4% for 2-layered and 4-layered 3D designs, respectively. |
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