Hardware-Software Co-Design for Brain-Computer Interfaces
| Autor: | Jan Vesely, Ioannis Karageorgos, Michael Wu, Abhishek Bhattacharjee, Marc Powell, Karthik Sriram, Rajit Manohar, David A. Borton |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Co-design Hardware architecture Signal processing business.industry Computer science Interface (computing) 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture Hardware software Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Architecture business Brain function Brain–computer interface |
| Zdroj: | ISCA |
| Popis: | Brain-computer interfaces (BCIs) offer avenues to treat neurological disorders, shed light on brain function, and interface the brain with the digital world. Their wider adoption rests, however, on achieving adequate real-time performance, meeting stringent power constraints, and adhering to FDA-mandated safety requirements for chronic implantation. BCIs have, to date, been designed as custom ASICs for specific diseases or for specific tasks in specific brain regions. General-purpose architectures that can be used to treat multiple diseases and enable various computational tasks are needed for wider BCI adoption, but the conventional wisdom is that such systems cannot meet necessary performance and power constraints. We present HALO (Hardware Architecture for LOw-power BCIs), a general-purpose architecture for implantable BCIs. HALO enables tasks such as treatment of disorders (e.g., epilepsy, movement disorders), and records/processes data for studies that advance our understanding of the brain. We use electrophysiological data from the motor cortex of a non-human primate to determine how to decompose HALO's computational capabilities into hardware building blocks. We simplify, prune, and share these building blocks to judiciously use available hardware resources while enabling many modes of brain-computer interaction. The result is a configurable heterogeneous array of hardware processing elements (PEs). The PEs are configured by a low-power RISC-V micro-controller into signal processing pipelines that meet the target performance and power constraints necessary to deploy HALO widely and safely. |
| Databáze: | OpenAIRE |
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