A 150 ns, 150 mW, 64K dynamic MOS RAM
| Autor: | M. Takada, S. Suzuki, T. Wada, S. Matsue, M. Kamoshida |
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| Rok vydání: | 1978 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 13:607-611 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thickness (t/SUB ox/) transistors as active elements. Also, the RAM with a newly designed sense amplifier has successfully been fabricated using only four photo resist masking processes. The access time and power dissipation are 150 ns and 150 mW, respectively, at the cycle time of 400 ns. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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