19.1 Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS
| Autor: | Akshat Boora, Rajesh Pamula, Fahim ur Rahman, Visvesh S. Sathe, Xun Sun |
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| Rok vydání: | 2019 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Operating frequency 02 engineering and technology Integrated circuit Topology law.invention Microprocessor CMOS law 0202 electrical engineering electronic engineering information engineering Minification Total energy Leakage (electronics) Voltage |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2019.8662486 |
| Popis: | Integrated circuits for ultra-low-power applications strive to minimize total system energy, while satisfying performance requirements. The supply voltage ($V_{dd}$) can be set to a Minimum Energy Point (MEP) [1, 2], where leakage and dynamic energy are suitably balanced. However, controlling operating frequency ($f_{c/k}$), while concurrently tracking a MEP sensitive to PVT and switching activity is not possible. Meanwhile, the traditional approach of locking to the minimum required frequency ($f_{targ}$), and adiusting $V_{dd}$to maintain timing slack precludes the possibility of minimum-energy computing. Therefore, there exists a need for a minimum-energy computing architecture that meets performance requirements. |
| Databáze: | OpenAIRE |
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