| Autor: |
K. Y. Au, Y.B. Yang, S Nathapong, Y. S. Koh Drake, P. L Ong Wilson, S. L. Kriangsak, Y. F. Zhang, J.D. Beleran |
| Rok vydání: |
2011 |
| Předmět: |
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| Zdroj: |
2011 IEEE 13th Electronics Packaging Technology Conference. |
| DOI: |
10.1109/eptc.2011.6184493 |
| Popis: |
Through silicon via (TSV) is a three-dimensional packaging technology involving vertical chips stacking using metal-filled via holes and bumps. TSV stacked chip drastically reduces interconnect distance than conventional multi-stack wire bond silicon chips, enabling faster speeds, lower power consumption and smaller microelectronic package size for 22nm tech node and below. TSI (Thru Silicon Interposer) enables interconnect pitch matching between a high I/Os top chip and low cost organic substrate and is crucial in mitigating risks of low K layer delamination and provide additional routing capability to enable the use of low cost organic substrate. This paper demonstrate with aid from finite element analysis, the daunting processibility challenges and reliability performance for a 2 die and 4 die thin die stacking on a strip organic substrate using standard flip chip machines in a mass production scenario. Critical factors such as 1× versus 2× reflow process flow, material properties fundamentals, bill of material (BOM), substrate & package structure design and its influence on thermo-mechanical stress, package warpage and joint cracks in conjunction with process breakthrough to enable multiple die stacking, multi-gap flux cleaning and capillary underfilling will be discussed in great details. In addition, Micro C4 solder bumps joints with TiW/Cu/Ni under bumps metallization (UBM) and TiW/Cu/Ni/Au bond pad were shown to be reliable with integrity of the UBM with regards to IMC growth and solder diffusion up to 1000 thermal cycles. Establishment of all these fundamental capabilities is required to strengthen the low cost high volume production capability for thru silicon stacking (TSS). |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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