Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS

Autor:	M. Ieong, C.Y. Sung, S. Deshpande, X. Chen, L. Deligianni, S. Cohen, C. Brodsky, S. Allen, C. Ouyang, Y. Li, B. Haran, A. Simon, B. Baker-O'Neal, C.-C. Yang, S. Rossnagel, R. Knarr, X. Shao, K. Wong, C. Sheraw, A. Topol
Rok vydání:	2006
Předmět:	Materials science chemistry.chemical_element Nanotechnology Tungsten Engineering physics chemistry.chemical_compound chemistry CMOS Silicide Parasitic element Current technology Node (circuits) Material properties Scaling
Zdroj:	2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
DOI:	10.1109/vlsit.2006.1705244
Popis:	A key challenge for high performance CMOS devices is the external parasitic resistance. This paper addresses scaling trends of contact level and discusses emerging constraints related to the properties of materials used in the current technology. Experimental and theoretical data presented herein are critical in understanding CA challenges beyond the 45 nm technology node and show great potential for copper as the alternative to tungsten process for CA metallization
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e8dd0225033aa30a83d1e7094b5c25d0 https://doi.org/10.1109/vlsit.2006.1705244 Zobrazit plný text záznamu