Quad-core radiation-hardened system-on-chip power architecture processor

Autor: Joe Stevenson, Lassa Marla J, Mary Hanley, Richard W. Berger, Brian Saari, Jason F. Ross, Gilliam Jane O, Ernesto Chan, Dan Pirkl, Patrick Fleming, Andrew T. Kelly, Steve A. Chadwick, Robert Lapihuska, Joseph R. Marshall, Richard Ferguson, Bin Li, Dave Moser, Hugh Miller, M. Graziano, Rickard Dale A, Daniel L. Stanley
Rok vydání: 2015
Předmět:
Zdroj: 2015 IEEE Aerospace Conference.
Popis: Based on the QorIQ® system-on-chip processor architecture from Freescale Semiconductor with additional unique features for space applications, the RAD55xxTM system-on-chip platform integrated circuit can be personalized into multiple processor solutions. The RAD55xx platform includes four 32/64 bit Power Architecture® processor cores, three levels of on-die cache memory, dual interleaved DDR3 DRAM controllers, data path acceleration architecture (DPAA) on-die hardware accelerators, a NAND Flash controller, and high I/O throughput based on serializer/deserializer high speed links. Manufactured at the IBM trusted foundry in 45nm silicon-on-insulator (SOI) process technology with copper interconnect and leveraging the radiation-hardened by design RH45TM technology, the RAD55xx platform optimizes power/performance to deliver processor throughput of up to 5.6 GOPS/3.7 GFLOPS, memory bandwidth of up to 102 Gb/s, and I/O throughput of up to 64 Gb/s. Each of the highly efficient RAD5500TM 64-bit cores offers direct addressability to 64 GB of memory, improves double precision floating point performance, and achieves 3.0 Dhrystone MIPS/MHz. The RAD55xx platform is designed for insertion into systems using the SpaceVPX standard, supporting the RapidIO data plane, SpaceWire control plane, and I2C utility plane. Architectural trades, the development methodology, technical challenges, and single board computer solutions are discussed.
Databáze: OpenAIRE