| Autor: |
D. Perry, Patrick Jaenen, Silvia Armini, G. Katti, Harold Philipsen, Youssef Travaly, Erik Sleeckx, D. Sabuncuoglu Tezcan, Nancy Heylen, I. Debusschere, N. Minas, G. Van der Plas, Y. Yang, Wouter Ruythooren, Serge Biesemans, P. Asimakopoulos, Chukwudi Okoro, Ming Zhao, Aleksandar Radisic, I. De Wolf, Anne Jourdain, P. Marchal, S. Thangaraju, J. Van Olmen, Philippe Soussan, E. Rohr, Augusto Redolfi, Riet Labie, Abdelkarim Mercha, M. Kostermans, Bart Swinnen, Tom Schram, T. Chiarella, Jun-Seok Cho, Eric Beyne, Shinichi Domae, A. Van Ammel, Dimitrios Velenis, Michele Stucchi |
| Rok vydání: |
2010 |
| Předmět: |
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| Zdroj: |
2010 Symposium on VLSI Technology. |
| Popis: |
3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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