Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
| Autor: | Ian Galton, Ritchie Zhao, Tutu Ajayi, Shaolin Xie, Christopher Batten, Paul Gao, Austin Rovinski, Chun Zhao, Steve Dai, Scott Davidson, Dustin Richmond, Aporva Amarnath, Zhiru Zhang, Khalid Al-Hawaj, Ronald G. Dreslinski, Luis Vega, Bandhav Veluri, Anuj Rao, Julian Puscar, Michael Taylor, Christopher Torng |
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| Rok vydání: | 2019 |
| Předmět: |
Router
Computer science 020208 electrical & electronic engineering Bandwidth (signal processing) Coremark 02 engineering and technology Parallel computing Giga Phase-locked loop Manycore processor RISC-V Scalability 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Electrical and Electronic Engineering |
| Zdroj: | IEEE Solid-State Circuits Letters. 2:289-292 |
| ISSN: | 2573-9603 |
| DOI: | 10.1109/lssc.2019.2953847 |
| Popis: | This letter presents a 16-nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak throughput of 695 Giga RISC-V instructions/s (GRVIS), a peak energy efficiency of 314.89 GRVIS/W, and a record 825 320 CoreMark benchmark score. Unlike previously reported [1] , this new score was obtained without modifying the core benchmark code. The main feature is the NoC architecture, which uses only $1881~\mu \text{m}^{2}$ per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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