Autor:	Andrzej Pulka
Rok vydání:	2018
Předmět:	System level modeling Computer science Programming language System level System verification computer.software_genre computer Formal verification
Zdroj:	2018 International Conference on Signals and Electronic Systems (ICSES).
DOI:	10.1109/icses.2018.8507290
Popis:	The paper presents a methodology of formal verification based on SAT solving technique. The author briefly recalls the JumpSAT algorithm. Then various aspects of the formal verification are presented and different approaches to the system level formal verification based on the JumpSAT algorithm are discussed on examples. Conclusions concerning the presented approach are given.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e79dcc05cca290d1f996f8f0e0f036ac https://doi.org/10.1109/icses.2018.8507290 Zobrazit plný text záznamu