0.5- mu m 2 M-transistor BiPNMOS channelless gate array
| Autor: | K. Maeguchi, Hiroyuki Hara, F. Sano, S. Kobayashi, Katsuhiro Seta, Hiroshi Momose, Yohji Watanabe, M. Noda, Tetsu Nagamatsu, Y. Niitsu, Takayasu Sakurai, Hiroyuki Miyakawa |
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| Rok vydání: | 1991 |
| Předmět: |
Computer science
Circuit design NAND gate Hardware_PERFORMANCEANDRELIABILITY PMOS logic law.invention Read-write memory Gate array law Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering Very-large-scale integration Magnetoresistive random-access memory Hardware_MEMORYSTRUCTURES business.industry Amplifier Bipolar junction transistor Transistor Electrical engineering Cutoff frequency Logic gate Inverter business Computer hardware Gate equivalent Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 26:1615-1620 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.98980 |
| Popis: | A channelless gate array has been realized using 0.5- mu m BiCMOS technology integrating more than two million transistors on a 14-mm*14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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