| Autor: |
S. Maeda, S. Maegawa, T. Ipposhi, H. Nishimura, H. Kuriyama, O. Tanina, Y. Inoue, T. Nishimura, N. Tsubouchi |
| Rok vydání: |
1994 |
| Předmět: |
|
| Zdroj: |
Proceedings of 1994 VLSI Technology Symposium. |
| DOI: |
10.1109/vlsit.1994.324421 |
| Popis: |
We propose a Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek alphabet /spl Phi/. It is built by penetration of the gate electrode (=word line) which has been formed beforehand. Application of the V/spl Phi/T for DRAM cell brings about cell size reduction to 50% and process simplification of about 10% at least. This is mainly because its bit line contact and the V/spl Phi/T are vertically aligned and storage node contact is eliminated. We have indicated that the V/spl Phi/T is an interesting candidate for the gigabit DRAM in view of size, cost and performance. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
