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VLSI-based systolic arrays have been promoted for almost a decade as efficient structures for many computationally-bound algorithms, such as the large class of matrix manipulation procedures. While they are very powerful conceptually, they suffer an inherent problem of requiring an enormous I/O bandwidth to sufficiently feed and drain the computational array. Satisfying this bandwidth, however, is difficult when the systolic structure is packaged in a pin-limited current technology carrier. Results of a study of the severity of this problem are presented, and data on the maximum size and throughput performance of such an array are provided. The pin limitation problem is solved by multiplexing operands onto and off of the chip, and the performance degrading effect of such multiplexing is obvious. > |
