Design and Implementation of High Speed and Energy Efficient 16 Bit 14 T CLA Using GDI Technique
| Autor: | M. Mohan Raju, Allenki Santhosh Kumar, Korra Ravi Kumar, Mittapally Sadanandam |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
Adder
Computer science 020208 electrical & electronic engineering Transistor 02 engineering and technology 020202 computer hardware & architecture law.invention 16-bit Arithmetic logic unit CMOS law Logic gate 0202 electrical engineering electronic engineering information engineering Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Block (data storage) Efficient energy use |
| Zdroj: | 2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC). |
| DOI: | 10.1109/iccic.2017.8524537 |
| Popis: | Carry look ahead adder (CLA) is the important block in arithmetic logic unit due to its high speed of operation. In this paper we propose a high speed and energy efficient CLA using Gate Diffusion Input (GDI) Technique with 14 Transistor to reduce the area. The simplest way to design an adder is to implement gates to yield the required logic function. In this paper the entire work is done in LTSpice 180nm technology, Xilinx14.7 ISE tool. The resulting analysis shows that the proposed methods are better than conventional CMOS technology. |
| Databáze: | OpenAIRE |
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