| Autor: |
G. Torelli, C. Calligaro, Pier Luigi Rolandi, A. Manstretta |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon. |
| DOI: |
10.1109/iciss.1996.552420 |
| Popis: |
This paper presents a sensing architecture for multilevel non-volatile memories. Sensing is carried out following a dichotomic algorithm, where each search step performs a number of parallel comparisons. Two sensing steps are able to detect as many as 16 levels (4 bits) when using three sense amplifiers per cell to be detected. The architecture is suitable for 16 Mcells (64 Mbit) EPROMs, where the memory cells are factory programmed to guarantee the tight threshold voltage distribution required for reliable store and sense. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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