Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems
Autor: | Andrew B. Kahng, Vaishnav Srinivas, Yenai Ma, Aditya Narayan, Furkan Eris, Ayse K. Coskun, Ajay Joshi |
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Rok vydání: | 2020 |
Předmět: |
Computer science
02 engineering and technology Network topology Computer Graphics and Computer-Aided Design Manufacturing cost 020202 computer hardware & architecture Reliability engineering Network planning and design Operating temperature 0202 electrical engineering electronic engineering information engineering Interposer Electrical and Electronic Engineering Routing (electronic design automation) Performance improvement Software |
Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:5183-5196 |
ISSN: | 1937-4151 0278-0070 |
DOI: | 10.1109/tcad.2020.2970019 |
Popis: | 2.5-D integration technology is gaining attention and popularity in manycore computing system design. 2.5-D systems integrate homogeneous or heterogeneous chiplets in a flexible and cost-effective way. The design choices of 2.5-D systems impact overall system performance, manufacturing cost, and thermal feasibility. This article proposes a cross-layer co-optimization methodology for 2.5-D systems. We jointly optimize the network topology and chiplet placement across logical, physical, and circuit layers to improve system performance, reduce manufacturing cost, and lower operating temperature, while ensuring thermal safety and routability. We also propose a novel gas-station link, which enables pipelined interchiplet links in passive interposers. Our cross-layer methodology achieves better performance-cost tradeoffs of 2.5-D systems and yields better solutions in optimizing interchiplet network and 2.5-D system designs than prior methods. Compared to single-chip systems, 2.5-D systems designed using our new approach achieve 88% higher performance at the same manufacturing cost, or 29% lower cost with the same performance. Compared to the closest state-of-the-art, our new approach achieves 40%–68% (49% on average) iso-cost performance improvement and 30%–38% (32% on average) iso-performance cost reduction. |
Databáze: | OpenAIRE |
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