Peak temperature reduction by optimizing power density distribution in 3D ICs with microchannel cooling
| Autor: | Cezary Maj, Piotr Zając, Andrzej Napieralski |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering Microchannel Computer cooling business.industry 020208 electrical & electronic engineering Three-dimensional integrated circuit 02 engineering and technology Dissipation Condensed Matter Physics Chip 01 natural sciences Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials Power (physics) Reduction (complexity) 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering Safety Risk Reliability and Quality business Power density |
| Zdroj: | Microelectronics Reliability. 79:488-498 |
| ISSN: | 0026-2714 |
| DOI: | 10.1016/j.microrel.2017.04.023 |
| Popis: | Liquid cooling with microchannels is a very attractive idea for 3D ICs which could help solving the problem of ever-increasing power dissipation due to its good cooling efficiency and potential scalability. However, this cooling method has some very different properties compared to the well-understood forced air convection. In particular, its cooling efficiency with respect to power variations in the chip is still not completely analyzed. Therefore, in this paper a thorough study of microchannel cooling efficiency as a function of intra- and interlayer power consumption variability is presented. We use a finite element method analysis to run a coupled thermo-fluidic simulation of a dedicated 3D chip model. An analytical analysis is also provided which calculates analytically the optimal power density profile along the channel. Then, steps necessary for finding the optimal power distribution for chip units are proposed. It is also shown that by appropriately managing the power density according to the proposed methodology, it is possible to significantly reduce the peak chip temperature. In particular, for a 3D chip including Intel's i7-6950X 10-core processor, a temperature reduction of 8.9 °C was achieved by a proper orientation of microchannels and another 5.8 °C reduction was obtained by optimally distributing power consumption between processor cores. |
| Databáze: | OpenAIRE |
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