Modeling the topography of uneven substrates post spin-coating
| Autor: | Werner Gillijns, Xiaoyu Piao, Frederic Lazzarino, Stefan Decoster |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Materials science 020209 energy Process Chemistry and Technology Process (computing) Mechanical engineering 02 engineering and technology 01 natural sciences Integrated circuit layout Surfaces Coatings and Films Electronic Optical and Magnetic Materials Tone (musical instrument) Chemical-mechanical planarization 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Materials Chemistry Wafer Electronic design automation Node (circuits) Electrical and Electronic Engineering Instrumentation Block (data storage) |
| Zdroj: | Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 36:03E102 |
| ISSN: | 2166-2754 2166-2746 |
| Popis: | The semiconductor industry has followed Moore's law for many decades and is currently preparing for high-volume manufacturing of the 7 nm technology node. To further scale down to the 5 nm technology node and below, research centers are constantly testing novel patterning and integration approaches. To enable a number of these new integration approaches, there is a growing need for a well-understood and well-controlled tone reversal technology. Tone reversal consists in inverting the tonality of all structures present on a wafer, e.g., turning a hole pattern into a pillar pattern. Examples of applications that advantageously integrate such tone reversal technology are multiple litho-etch block patterning, the fully self-aligned block concept, and the direct metal etch approach. A critical step in the tone reversal process is to achieve a good wafer planarization, i.e., limited wafer topography. This can be done by chemical mechanical polishing after filling the patterned features that need to be tone inverted. However, a more promising approach is to reduce the topography by using a planarizing spin-coating process to fill the patterns. Material vendors and research groups have done tremendous efforts to understand and improve the quality (uniformity, planarity, etch resistance, etc.) of spin-coating processes. When a spin-coating process is used to fill a given patterned structure, it is known that the degree of planarization is impacted by a set of parameters such as pattern width and density. However, it is not clear yet what the exact functional dependence is. In this work, the authors first present an experimental study of the planarization behavior of spin-coated materials as a function of pattern width, depth, and density. The authors observed a strong dependency of the width and the density of the patterns on the wafer topography post spin-coating, while the depth, within the boundaries of this study, showed no significant impact. The most striking result was the observation of the linear relationship between the pattern density difference between two areas and the relative height difference of those areas after spin-coating. Second, based on these experimental observations, the authors present a model that predicts the remaining wafer topography post spin-coating. The model calculates the topography for a given set of structures, using only one parameter as input. This parameter is a fixed number for a specific spin-coating process and is called the planarization length λ. The authors demonstrate that this model is capable of reproducing and predicting the experimentally measured height profiles on complex patterned structures for different spin-coating processes. These calculations can be done with commercially available electronic design automation software. Therefore, this model can become a powerful tool in mask design, both for applications based on tone reversal, and, in general, for patterning processes that make use of spin-coated materials.The semiconductor industry has followed Moore's law for many decades and is currently preparing for high-volume manufacturing of the 7 nm technology node. To further scale down to the 5 nm technology node and below, research centers are constantly testing novel patterning and integration approaches. To enable a number of these new integration approaches, there is a growing need for a well-understood and well-controlled tone reversal technology. Tone reversal consists in inverting the tonality of all structures present on a wafer, e.g., turning a hole pattern into a pillar pattern. Examples of applications that advantageously integrate such tone reversal technology are multiple litho-etch block patterning, the fully self-aligned block concept, and the direct metal etch approach. A critical step in the tone reversal process is to achieve a good wafer planarization, i.e., limited wafer topography. This can be done by chemical mechanical polishing after filling the patterned features that need to be tone inve... |
| Databáze: | OpenAIRE |
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