| Popis: |
The article presents for the first time a gallery of 3D boundary surfaces of a multi-value memory cell. In the analysis, we chose such sizes of parasitic elements on the chip, in which there are no stable limit cycles present in the memory, assuming that the absence of stable limit cycles will greatly simplify the transcription of information in the memory. However, this fact was not confirmed and the 3D gallery of boundary surfaces points to the need to know the boundary surface for each case of changing the size of parasitic capacitances on the chip. This will make it possible to explain the memory failure associated with, for example, a change in technology in the memory production. At the same time, visualization of boundary surfaces, attractors or chaotic attractors using virtual reality technologies is offered for another technical activities. |
