Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175 $^{\circ}\hbox{C}$
| Autor: | Lawrence T. Clark, E. J. Bawolek, Daniel Toy, Zi Li, David R. Allee, R. Shringarpure, Sameer M. Venugopal |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Amorphous silicon
Materials science Silicon business.industry Transistor Spice Electrical engineering chemistry.chemical_element Biasing Hardware_PERFORMANCEANDRELIABILITY Electronic Optical and Magnetic Materials law.invention chemistry.chemical_compound chemistry Thin-film transistor law Logic gate Hardware_INTEGRATEDCIRCUITS Optoelectronics Degradation (geology) Electrical and Electronic Engineering business Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Electron Devices. 54:1781-1783 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/ted.2007.899667 |
| Popis: | This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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