| Autor: |
Youngcheol Chae, Taewoong Kim, Yigi Kwon, Nan Sun |
| Rok vydání: |
2021 |
| Předmět: |
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| Zdroj: |
IEEE Solid-State Circuits Letters. 4:166-169 |
| ISSN: |
2573-9603 |
| DOI: |
10.1109/lssc.2021.3114318 |
| Popis: |
This letter presents a two-stage dynamic amplifier that achieves the high dc gain and PVT robustness of the residue amplifier in a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier operates in a closed-loop configuration and does not require further calibration. The pipelined SAR ADC occupies 0.065 mm2 in a 65-nm CMOS process. It achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 68.8 dB at a sampling rate of 20 MS/s and draws 348 $\mu \text{W}$ from a 1.2-V supply. This corresponds to a Schreier FoM of 173.4 dB and a Walden FoM of 7.7 fJ/conv.-step. Furthermore, it maintains SNDRs over various sampling rates from 1 to 20 MS/s and its power consumption is scaled linearly. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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