Total Performance of 32-nm-Node Ultralow-$k$/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica $(k = \hbox{2.1})$

Autor:	Shuichi Saito, Y. Kawashima, S. Chikaki, R. Hayashi, N. Oda, T. Suzuki, T. Kubota, N. Nakamura, K. Tomioka, A Gawase, S. Nakao, E. Soda, J. Nogawa
Rok vydání:	2010
Předmět:	Interconnection Materials science Chemical engineering Chemical-mechanical planarization Electronic packaging Copper interconnect Low-k dielectric Nanotechnology Integrated circuit packaging Electrical and Electronic Engineering Porosity Capacitance Electronic Optical and Magnetic Materials
Zdroj:	IEEE Transactions on Electron Devices. 57:2821-2830
ISSN:	1557-9646 0018-9383
Popis:	The total performance of low-k/Cu interconnects featuring short turnaround-time (TAT) silylated scalable porous silica (Po-SiO, k = 2.1) with high porosity (50%) is demonstrated. The TAT for the film formation process including silylation treatment is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, a 140-nm-pitch dual-damascene structure is successfully achieved. The wiring capacitance showed 10% reduction, compared to the conventional porous SiOC (ULK, k = 2.65). Sufficient interconnect reliability and packaging characteristics for the circuit-under-pad structure are also obtained. The predicted circuit performance was 8% higher than ULK in the 32-nm node.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e5623a3e14177c02de365bf919da7d50 https://doi.org/10.1109/ted.2010.2066568 Zobrazit plný text záznamu