A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme
| Autor: | Sung-Gi Ahn, Yong-ki Kim, Ryu Ye-Sin, Kyomin Sohn, Ki-Chul Chun, Dong Hak Shin, Byung-Kyu Ho, Jae-Won Park, Ji-Hye Kim, Chi Sung Oh, Byoung Mo Moon, Jae-Seung Jeong, Nam Sung Kim, S.J. Ahn, Jun Jin Kong, Seong-Jin Cho, Jun Gyu Lee, Jung-Bae Lee, So-Young Kim, Young Yong Byun, Seouk-Kyu Choi, Jae-Hoon Lee, Woo Seunghan, Soo-Young Kim, Min-Sang Park, Beomyong Kil |
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| Rok vydání: | 2021 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Computer science business.industry 020208 electrical & electronic engineering Bandwidth (signal processing) 02 engineering and technology Chip Die (integrated circuit) 0202 electrical engineering electronic engineering information engineering Bandwidth (computing) Bit error rate Electrical and Electronic Engineering business Power network design Computer hardware Dram System bus Block (data storage) |
| Zdroj: | IEEE Journal of Solid-State Circuits. 56:199-211 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging from data-path architecture, through-silicon via (TSV) placement, and TSV-PHY alignment. A power TSV placement in the middle of array and at the chip edge along with a dedicated top metal for power mesh improves power IR drop by 62%. An on-die ECC (OD-ECC) scheme featuring a self-scrubbing function is designed to be orthogonal to system ECC. An uncorrectable bit error rate (UBER) is improved by 105 times with the proposed OD-ECC and scrubbing scheme. A memory built-in self-test (MBIST) block supports low-frequency cell and core test in a parallel manner and all channel at-speed operation with adjustable ac parameters. The proposed parallel-bit MBIST reduces test time by 66%. A 16-GB HBM2E fabricated in the second generation of 10-nm class DRAM process achieves a bandwidth up to 640 GB/s (5 Gb/s/pin) and provides a stable bit-cell operation at a high temperature (e.g., 105 ° C). |
| Databáze: | OpenAIRE |
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