| Popis: |
The growth in computational power has resulted in a divergence in CPU design from clock acceleration to parallelization techniques (multi-core processors) to improve computation and energy performance. Lab-based learning of computer performance in multiple-processor systems is complicated when most labs are equipped with now nearly dated single-core machines. An alternative is to study multi-processor performance using high performance computing (HPC) clusters. Not all labs can afford their own HPC machine however. A lab-based course in Computer Architecture for Electrical and Computer Engineering Technology students has been offered for four semesters, including a high performance computing laboratory experience. Recently the course was offered at a satellite campus located roughly 120 miles from the main campus, and the HPC system. This paper documents early experiences with using HPC hardware and concepts in a laboratory environment to demonstrate multiprocessor performance dynamics. Combined with the topics of instruction pipelining, the memory hierarchy, and I/O performance modeling, students have initially reacted positively, gaining an appreciation of performance speedup and its limiting factors. Suggestions for similar HPC implementations on small and medium scales are also provided. |
