| Autor: |
L. O'Donnell, V. Sundaresan, Brian J. Campbell, Tuan Do, G. Yee, R. Blake, Donald A. Priore, N. Bunger, Daniel C. Murray, E. Supnet, D. Kidd, Ingino Joseph M, D. Rodriguez, M. Pearce, G. Yiu, Sribalan Santhanam, Jong Lee, M. Carlson, K. Anne, V. von Kaenel, J. Cheng, C. Vo, Robert Rogenmoser, S. Nishimoto, R. Wen, Dongwook Suh, Zongjian Chen, David A. Kruckemyer, M. Panich, Daniel W. Dobberpuhl, M. Oykher, R. Allmon |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185). |
| DOI: |
10.1109/vlsic.2001.934209 |
| Popis: |
The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD's Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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