| Popis: |
The comparator is the basic block for data converter circuits, designing modern analog and mixed-signal systems, for example, telecommunications that interface with sensing circuits. Several analog to digital converters (ADCs) require low-power, high-speed comparators through less area of chip. The spin device-based self-calibrated comparators are accustomed to design high-speed, low-offset and power ADCs. This paper presents two spin devices based on self-calibrated comparator, which is an area and power efficient compared with other comparators. Our proposed self-calibrated comparator consumes 1.3 µW power and 0.0272 fJ energy at a supply voltage of 0.75 V. The spin devices (MTJ and a Strip), SPICE compatible model-based Verilog-A language and PTM CMOS 45 nm model are used to simulate its performance, like the power and delay, and compared it with dynamic comparators. |
