180nm FRAM reliability demonstration with ten years data retention at 125°C

Autor:	P. Ndai, Theodore S. Moise, Hugh P. McAdams, J. Rodriguez-Latorre, M. Ball, J. Rodriguez, Tamer San, Sudhir K. Madan, C. Zhou, Antonio Guillermo Acosta, Scott R. Summerfelt, K. R. Udayakumar, Archana Venugopal
Rok vydání:	2013
Předmět:	Engineering Reflow soldering Reliability (semiconductor) CMOS business.industry Margin (machine learning) Electronic engineering Bit error rate Data retention business Error detection and correction Signal
Zdroj:	2013 IEEE International Reliability Physics Symposium (IRPS).
Popis:	Reliability of a 2T-2C, 448kbit FRAM embedded within 180nm CMOS is presented. The results indicate a 10-year, 125°C data retention capability for this technology. Further, sufficient signal margin remains for sensing following 260°C Pb-free solder reflow step demonstrating that code data can be stored through the board-attach process. A new margin test approach, which enables depolarization effects to be quantified, has been developed. A model to estimate device fail rate based on array size, word length, error correction circuitry and bit error rate is also described.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e30e278d394659eff316d45f6a107fae https://doi.org/10.1109/irps.2013.6532102 Zobrazit plný text záznamu