7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme
| Autor: | Takashi Nakada, Atsushi Kawasumi, Shinobu Fujita, Hiroyuki Hara, Keiko Abe, Junichi Ito, Naoharu Shimomura, Satoshi Takaya, Eishi Arima, Kazutaka Ikegami, Keiichi Kushida, Hiroki Noguchi, Hiroshi Nakamura |
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| Rok vydání: | 2016 |
| Předmět: |
Computer science
Cache coloring CPU cache 02 engineering and technology Parallel computing Cache-oblivious algorithm Cache pollution 01 natural sciences Non-uniform memory access Write-once 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Interleaved memory Static random-access memory Memory refresh Cache algorithms Computer memory 010302 applied physics Random access memory Magnetoresistive random-access memory Hardware_MEMORYSTRUCTURES Memory hierarchy business.industry Cache-only memory architecture Uniform memory access Semiconductor memory MESIF protocol Memory map 020202 computer hardware & architecture Mass storage Resistive random-access memory Non-volatile memory Shared memory Embedded system Non-volatile random-access memory Page cache Cache business |
| Zdroj: | ISSCC |
| Popis: | Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D-cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT-MRAM has achieved sub-4ns read and write accesses with perpendicular magnetic tunnel junctions (p-MTJ) [1–2]. Furthermore, mature integration processes have been developed and 8Mb STT-MRAM with sub-5ns operation has shown high reliability [3]. Moreover, because of its non-volatility, STT-MRAM can reduce operation energy by more than 81% compared to SRAM for cache [1]. This paper presents STT-MRAM-based last level cache memory (LLC) including MRAM memory core, peripherals and cache logic circuits, using novel power optimization with high-speed power gating (HS-PG),considering processor architectures and cache memory accesses. The STT-MRAM-based cache has high reliability to reduce the write-error rate with novel write-verify-write. Furthermore, a read-modify-write scheme is implemented to reduce active power without penalty. Figure 7.2.1 presents a block diagram of a 4Mb STT-MRAM based cache. |
| Databáze: | OpenAIRE |
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