Realization of Digital Balance Algorithm Based on HLS for High Precision Impedance Analyzer
| Autor: | Zixin Wang, Yingfeng Ding, Qinglian Yang, Junlong Huang, Mushui Zhang, Jiarong Chen |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Computer science
Hardware description language Computer Science::Hardware Architecture Ternary search visual_art Electronic component visual_art.visual_art_medium Waveform Successive parabolic interpolation computer Realization (systems) Electrical impedance Algorithm computer.programming_language Interpolation |
| Zdroj: | 2021 IEEE International Conference on Computer Science, Electronic Information Engineering and Intelligent Control Technology (CEI). |
| DOI: | 10.1109/cei52496.2021.9574455 |
| Popis: | Aiming to improve the accuracy and calculation speed of high precision impedance analyzer efficiently, we developed a digital balance algorithm module of the impedance analyzer based on High-Level Synthesis (HLS). The function of the proposed algorithm is realized by parabolic interpolation method with a faster convergence speed than the previous ternary search method. Then the digital balance algorithm based on C language is converted into a hardware algorithm accelerator based on Hardware Description Language (HDL) through HLS. After generating the IP core of the digital balance algorithm module and constructing the whole hardware system, we tested the properties of the design by measuring several electronic components respectively, where the digital balance algorithm is based on different methods. Through observing the waveform of the bridge balance point, we conclude that the amplitude of the balance point after digital balance adjustment is below 16mV with a shorter balance time about 450ms, which verify the reliability and the optimization of the implementation of the proposed algorithm by HLS. |
| Databáze: | OpenAIRE |
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