Design of high PSRR folded cascode operational amplifier for LDO applications
| Autor: | Harsh Gupta, Navaid Z. Rizvi, Gaurav Kumar Mishra, Santosh Kumar Patnaik |
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| Rok vydání: | 2016 |
| Předmět: |
Engineering
Power supply rejection ratio business.industry 020208 electrical & electronic engineering Electrical engineering Phase margin Differential amplifier 020206 networking & telecommunications Operational amplifier applications 02 engineering and technology law.invention law 0202 electrical engineering electronic engineering information engineering Operational amplifier Electronic engineering Cascode business Direct-coupled amplifier Gain–bandwidth product |
| Zdroj: | 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). |
| DOI: | 10.1109/iceeot.2016.7755591 |
| Popis: | This paper presents a novel CMOS folded cascode operational amplifier that leads to high PSRR and provides gain nearly equal to that of a two stage op-amp. The proposed design is implemented in GPDK 0.18μm CMOS technology. This op-amp uses a folded cascode structure in the output stage combined with the differential amplifier having PMOS input transistors to achieve good input common mode range and lower flicker noise. It has an important feature that it allows the input common mode level close to supply voltage. The proposed topology improves the PSRR of op-amp which can be used for LDO applications. Simulations using Cadence under 1.8 V show a DC gain of 72.0404 dB and a phase margin of 62.4636 degree at a unity gain bandwidth of 13.33 MHz with the power consumption smaller than 0.13 mW along with a PSRR of 72.0966 dB. The layout of the design shows that the area acquired on the chip is approximately equal to 8897.27 μm2. |
| Databáze: | OpenAIRE |
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