Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

Autor: K.J. Choi, Chadwin D. Young, J. Oh, Y.N. Tan, Rajarao Jammy, Byung Jin Cho, Gennadi Bersuker, P. Sivasubramani, D. Q. Kelly, Se Hoon Lee, C. Park, P. Y. Hung, Niti Goel, J. Price, Byoung Hun Lee, P. Lysaght, Jiacheng Huang, Dawei Heh, H.R. Harris, Paul Kirsch, David Gilmer, Prashant Majhi, H-H. Tseng, Chanro Park
Rok vydání: 2008
Předmět:
Zdroj: 2008 Symposium on VLSI Technology.
DOI: 10.1109/vlsit.2008.4588571
Popis: For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91 nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5times Si), and low subthreshold slope (73 mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.
Databáze: OpenAIRE