Autor:	Przemyslaw Bakowski, Jean-Paul Caïsso, Frédéric Igier, Frédérique Bouchard
Rok vydání:	1995
Předmět:	Engineering Application-specific integrated circuit Computer architecture business.industry VHDL Electronic engineering Hardware_ARITHMETICANDLOGICSTRUCTURES business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer Hardware_LOGICDESIGN computer.programming_language
Zdroj:	Current Issues in Electronic Modeling ISBN: 9781461359890
DOI:	10.1007/978-1-4615-2335-2_3
Popis:	This paper presents the evolution of an emerging VHDL modeling methodology, called VITAL, which aims at writing accurate and portable VHDL models for ASIC gate libraries. We also provide here a comparison of VITAL performances to classical simulations.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e11eef972c9320e1639a0c7e3fe8972b https://doi.org/10.1007/978-1-4615-2335-2_3 Zobrazit plný text záznamu