| Autor: |
Young-Gun Ko, Jeongmin Choi, Y. Yasuda-Masuoka, Kyunghoon Jung, Heebum Hong, Sungil Jo, Jae-Hun Jeong, Minseong Lee, Young-Ho Lee, Sihyung Lee, Ju Youn Kim, Gitae Jeong, Kihwang Son, Ho Lee, Byungha Choi, Hyung-Jong Lee, Chunghwan Shin, Jong Mil Youn, Sung Won Kim, Jae-Chul Kim |
| Rok vydání: |
2020 |
| Předmět: |
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| Zdroj: |
2020 IEEE International Electron Devices Meeting (IEDM). |
| Popis: |
In this paper, we demonstrate state of the art 5nm technology (5LPE) having co-optimization process for Dual CPP (Critical Poly-Pitch) technology to maximize Product Power-Performance-Area by separating both high speed and low power blocks. As a result, 5LPE successfully has 10% speed gain or 20% power gain and 0.75x logic area over our previous 7nm technology [1] with more advanced FinFET technology having EUV process and design optimization. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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