Evaluation of logic SER for a network processor and the use of targeted hardening to improve system SER performance

Autor:	L. Keegan, Karthik Chandrasekharan, J. K. Wang, Balaji Narasimham, Gregory Djaja, S. Risch, J. Spillane
Rok vydání:	2013
Předmět:	Engineering business.industry Network processor Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design law.invention Logic synthesis Soft error law Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering business Computer hardware Flip-flop Hardware_LOGICDESIGN Hardening (computing)
Zdroj:	2013 IEEE International Reliability Physics Symposium (IRPS).
DOI:	10.1109/irps.2013.6531990
Popis:	Chip-level logic masking simulations were performed on a network processor with ~1.75M flip-flops to identify the masking factors and the functional blocks that contribute to most errors. Results indicate that most errors originate from a few functional blocks, and that targeted hardening of the flip-flops can significantly improve the overall system SER at very low area, speed, and power penalties. A novel hysteresis-based DFF hardening technique is presented with experimental results from a 28 nm test chip design.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e0ac3d549085783c357a97af31c16013 https://doi.org/10.1109/irps.2013.6531990 Zobrazit plný text záznamu