A Single-chip, 1.2 Ghz, PLL frequency synthesizer Using Reduced Capacitance, dual gate, BiCMOS technology

Autor:	D. Stolfa, David F. Moeller, K. Huehne, K. Stierman
Rok vydání:	2005
Předmět:	Frequency synthesizer Phase-locked loop Single chip Materials science Direct digital synthesizer Electronic engineering Dual gate Capacitance Bicmos technology
Zdroj:	Proceedings of the IEEE Custom Integrated Circuits Conference.
DOI:	10.1109/cicc.1992.591832
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::e085975914fa65262ff4a2f75577b2b0 https://doi.org/10.1109/cicc.1992.591832 Zobrazit plný text záznamu